`timescale 1ns/1ns  module top_module(      input [4:0] in,     output out_and,     output out_or,     output out_xor );     wire b0, b1, b2, b3, b4;     assign b0 = in & 1;     assign b1 = (in & 2) >> 1;     assign b2 = (in & 4) >> 2;     assign b3 = (in & 8) >> 3;     assign b4 = (in & 16) >> 4;     assign out_and = b0 & b1 & b2 & b3 & b4;     assign out_or = b0 | b1 | b2 | b3 | b4;     assign out_xor = b0 ^ b1 ^ b2 ^ b3 ^ b4;  endmodule